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Associate Professor, Department of Electrical Engineering and Computer Science
University of Michigan, Ann Arbor
Title: Sparse Spiking Neuromorphic Hardware for Computer Vision
Abstract: Hardware-based neuro-inspired computing accelerators will likely become an essential part of future mobile and autonomous devices to enable low-power and real-time cognitive processing, such as computer vision and voice recognition. To realize real-time processing, the accelerator design can be massively parallelized and tailored to the underlying algorithms. However, massive parallelism alone does not address the scalability and efficiency needed by future systems. In this work, we make use of sparsity in designing a spiking sparse coding accelerator and a sparse convolutional neural network accelerator. By enabling new architectures and substantially reduce their complexity, sparsity helps deliver the next order of magnitude improvement in performance and efficiency of machine learning hardware.
Bio: Zhengya Zhang received the B.A.Sc. degree in computer engineering from the University of Waterloo, Canada, in 2003, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 2005 and 2009, respectively. Since 2009, he has been with the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor, where he is currently an Associate Professor. His research is in the area of low-power and high-performance VLSI circuits and systems for computing, communications and signal processing. Dr. Zhang received the NSF CAREER Award in 2011, the Intel Early Career Faculty Award in 2013, the David J. Sakrison Memorial Prize for outstanding doctoral research in EECS at UC Berkeley in 2009, and the Best Student Paper Award at the Symposium on VLSI Circuits in 2009. He serves as an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems.