This is a past event.

ICC member and lecturer, Shuai Wang (CS) will present "Low Power Aging-AwareOn-Chip Memory Structure Design by Duty Cycle Balancing".

Refreshments will be served.

Abstract: The degradation of CMOS devices over the lifetime can cause severe threat to the system performance and reliability at deep submicron semiconductor technologies. The negative bias temperature instability (NBTI) is among the most important sources of the aging mechanisms. Applying the traditional guardbanding technique to address the decreased speed of devices is too costly. On-chip memory structures, such as register files and on-chip caches, suffer a very high NBTI stress. In this talk, the proposed aging-aware design to combat the NBTI-induced aging in integer register files, data caches and instruction caches in high-performance microprocessors will be discussed. The proposed aging-aware design can mitigate the negative aging effects by balancing the duty cycle ratio of the internal bits in on-chip memory structures. Besides the aging problem, the power consumption is also one of the most prominent issues in microprocessor design. Therefore, applying the low power schemes to different memory structures under aging-aware design was further proposed. The low power aging-aware design can achieve a significant power reduction, which will further reduce the temperature and NBTI degradation of the on-chip memory structures.